CMOS logic is the technology of choice in today's very large scale integration (VLSI) digital integrated circuits. The low power dissipation and circuit density of CMOS logic allows greater circuit complexity than is possible with competing technologies. However, the interface required between the CMOS logic in the integrated circuits and the "outside" world is a CMOS incompatible standard. At present, TTL logic levels are used as the standard. In CMOS a logical "0" is represented by a voltage less than half of the power supply voltage (typically &lt;2.5 volts) while a logical "1" is represented by a voltage greater than half the power supply voltage (&gt;2.5 volts.) TTL requires a logical "1" to be greater than 2 volts and a logical "0" to be less than 0.8 volts. A well known circuit which translates the TTL logic levels to CMOS is diagrammed in FIG.1. The buffer 10 is a static (non-clocked) scaled inverter in which the size of the N-channel resistor 11 is five times the size of the P-channel transistor 12. The sizing (scaling) of the transistors establishes the threshold of the buffer 10 to be approximately 1.4 volts, or half-way between 2 and 0.8 volts, the worst-case TTL logic voltage levels. However, this design is sensitive to processing variations in manufacturing (mobility variation, device threshold voltage variation, gate oxide thickness variation, physical transistor size distortion, etc.), operating temperature and input supply voltage (Vdd) variations to the buffer 10. These variations cause the threshold voltage to deviate over an exemplary range of 1.1 to 1.8 volts. Further, it is understood that the P-channel transistor 12 is inherently slower than the N-channel transistor 11 by a factor of 2.5 to 3 due to the mobility difference between P and N type semiconductors. Scaling of the N-channel transistor 11 by a factor of five larger than the P-channel transistor 12 aggravates the speed difference between the transistors 11, 12 to, roughly, a factor of 15. This speed difference causes propagation delay skew where the delay through the buffer 10 for an input signal having a high-to-low transition is much longer than that for an input signal having a low-to-high transition.
Another TTL to CMOS input buffer is diagrammed in FIG. 2. Buffer 20 is a two stage static TTL to CMOS input buffer utilizing the same scaled inverter approach of FIG. 1 (transistors 21, 22) in a first stage 20a but with transistor 23 operating as a level shifter, shifting the threshold voltage of stage 20a downward. The second stage, inverter 24, buffers the output of stage 20a and co-operates with stage 20a to achieve the desired threshold voltage of the buffer 20. Since this design is substantially the same as the scaled inverter of FIG. 1, the problems of variation in threshold voltage with process, temperature and input supply voltage variations still occur.